1. Field of the Invention
The present invention relates to a modulation circuit for generating and outputting a plurality of pulse signals at a predetermined period and an image display and a modulation method using the modulation circuit, more particularly relates to a modulation circuit of a driving signal for a light emitting diode (LED) or an organic electroluminescence (EL) element, and an image display comprising an LED or an organic EL element.
2. Description of the Related Art
Since the invention of the blue LED, LED color displays that use LEDs to form pictures by pixels emitting the three primary colors have been widely and generally fabricated. An LED is highly durable can be used semipermanently, so is optimal for long-term use outdoors. Therefore, LEDs have been extensively used for large-scale displays in stadiums and event sites and for information display panels or advertisements on sides of buildings and inside railway stations. In recent years, along with the increasing luminance and lower prices of blue LEDs, such LED color displays have been spreading rapidly.
FIG. 1 is a view of a drive circuit of an LED forming a pixel of an LED display.
In FIG. 1, reference numeral 100 indicates a drive circuit and 200 an LED. In addition, Spx represents a video signal supplied to an individual pixel, and Id a current flowing through the LED 200, respectively.
The drive circuit 100 outputs a current according to the video signal Spx to the LED 200, while the LED 200 emits light according to the supplied current. An LED display is comprised of exactly the same number of circuits consisting of the drive circuits 100 and LEDs shown in FIG. 6 as that of the pixels. By making the LEDs of the pixels emit light with luminances according to the video signals Spx supplied to the pixels, a person viewing the screen can recognize a picture. The video signal Spx supplied to each pixel is generally input to the drive circuit 100 as a digital value of a certain number of bits.
FIG. 2 is a view of the waveform of the current flowing through the LED 200 in FIG. 1.
In FIG. 2, the ordinate indicates the current flowing through the LED 200 by a relative value, while the abscissa indicates time by a relative value. In addition, Ipulse indicates the peak value of the waveform of the pulse-shaped current flowing through the LED, tw the time width of the pulse portion, and T the period of the waveform.
As shown in FIG. 2, the current flowing through the LED forming a pixel of an LED display has a periodic pulse-like waveform. The luminance is controlled by pulse width modulation to make the pulse width tw variable.
In principle, the current flowing through the LED is a direct current. It is possible to change the current value in accordance with the video signal Spx to adjust the luminance, but in this case, it is necessary to finely control the current value by the drive circuit. There is the disadvantage that the circuit for this control ends up increasing the number of parts. It is easier to increase the resolution of the time than the resolution of the current value, so in general the pulse width modulation system such as shown by the current waveform of FIG. 2 is adopted.
Due to the nature of human senses, the luminance of light blinking in a manner staying lit for less than {fraction (1/60)} of a second is perceived to have a constant luminance. Therefore, even an LED is driven by a current of the waveform shown in FIG. 2, if the period T of the current is shorter than the aforesaid time, the blinking light from the LED can be made to be perceived by people as light of a constant luminance.
Further, generally, the magnitude of the luminance of an LED perceived by the human senses is proportional to the current flowing through the LED averaged over time. Therefore, the luminance changes in proportion with the duty of the pulse current.
The level of a video signal input to an LED display, however, is normalized in advance to match the luminance characteristics of a cathode ray tube (CRT). If such a video signal is input as it is to an LED, which has different luminance characteristics from a CRT pixel, the following problem arises.
FIG. 3 is a view of the relation of the luminances of an LED and CRT pixel with the level of an input signal.
In FIG. 3, the ordinate represents the luminance of an LED or CRT pixel by a relative value, while the abscissa represents the level of the signal input to an LED or a CRT pixel by a relative value. The curves indicated by A and B show the luminance characteristics of a CRT pixel and an LED, respectively.
Note that for the luminance characteristic A of a CRT pixel, the level of the video signal is expressed by voltage, while for the luminance characteristic B of an LED, the level of the video signal is expressed by the current flowing through the LED.
As shown in FIG. 3, the luminance of an LED has a linear relationship with the signal level, while the luminance of the CRT pixel has a nonlinear relationship with the signal level. In general, the luminance of a CRT pixel is proportional to the 2.2th power of the voltage level of the video signal. If a current proportional to a video signal normalized to match such a characteristic is directly supplied to an LED, the LED appears brighter than a CRT pixel in the region of low output of light, but appears darker than a CRT pixel in the region of high output of light. Consequently, a picture formed by such pixels has a ratio of luminance of the bright portions and dark portions different from the original picture, so looks unnatural to the viewer.
In order to solve this problem, in an LED display of the related art, a signal corrected to eliminate the influence due to the above luminance characteristic of the video signal is input to the drive circuit 100 as the above video signal Spx. Specifically, for example, when driving an LED of a linear luminance characteristic by a video signal produced to match with CRT pixel emitting light of a luminance proportional to the 2.2th power of the signal level, a signal proportional to the 2.2th power of the video signal is generated to drive the LED.
However, if the bit length of the original video signal is not sufficiently large, the binary data obtained by raising this digitalized image data to the 2.2th power is incapable of expressing fine changes of value in the region where the value of the original video signal is small. In other words, if the bit length of the digitalized video signal is small, the grey scale ends up rough in the low luminance region resulting in an unnatural picture. In order to avoid such a problem, it is necessary to increase the bit length of the video signal. Specifically, in an LED display of the related art, it is necessary to generate a video signal of a length of 12 to 16 bits to reproduce a picture which had been expressed by a video signal of a length of 8 bits in the case of a CRT. If the bit length of the video signal is increased in this way, the bit length of the pulse width modulation circuits for driving the LEDs also has to be increased, so the overall circuit scale becomes larger and the cost and power consumption rise.
Further, the pulse-like waveform shown in FIG. 2 is generally generated by counting a clock signal serving as a time reference. Increasing the bit length of a video signal means increasing the number of times to count the clock signal by that extent, so when using a clock signal of the same frequency, the period T of pulse width modulation ends up longer. For example, when generating and modulating the pulse width of a 12-bit video signal, 4 bits larger than an 8-bit video signal, and comparing them with the same frequency of the clock signal, the period T of pulse width modulation becomes 16 times that of an 8-bit video signal. Since the period T of pulse width modulation is set using the characteristic of the human senses described above, if this period is too long, xe2x80x9cflickeringxe2x80x9d where the blinking of the light will be perceived by the human eye will be caused and the picture will become hard to view. Furthermore, this flickering by nature is more noticeable to the human eye in an LED display compared with a CRT, so the period T of pulse width modulation has to be several times higher than that of the usual refresh rate, for example, for example {fraction (1/50)} of a seconds.
To increase the bit length of a video signal and shorten the period T of pulse width modulation, it is enough to increase the frequency of the clock signal used in the pulse width modulation circuit, but this has the disadvantage of increasing the power consumption of the circuit. Further, as it is difficult to further increase the current frequency of 10 to 20 MHZ 10 or more fold, there is a limit to increasing the frequency of the clock signal.
An object of the present invention is to provide a modulation circuit capable of high resolution pulse width modulation while keeping down the increase of the number of bits and an image display provided with the modulation circuit.
In order to achieve the above object, according to a first aspect of the present invention, there is provided a modulation circuit for outputting a pulse signal modulated according to a value of a binary code, comprising a selecting means for dividing the binary code from the most significant bit to the least significant bit into a plurality of binary codes and selecting and outputting the divided binary codes produced by this division in a preset order and a pulse outputting means for receiving the divided binary codes obtained from the selecting means and outputting a plurality of pulse signals having a pulse width and level corresponding to the divided binary codes by a predetermined period.
According to the modulation circuit of the present invention, the binary code for modulating the pulse signal is divided into a plurality of codes from the most significant bit to the least significant bit. The plurality of binary codes obtained by this division are defined as divided binary codes. These divided binary codes are selected and output to the pulse outputting means in a preset order by the selecting means. Then, the pulse outputting means generates and outputs a plurality of pulse signals having pulse widths and levels corresponding to the divided binary codes at a predetermined period.
Preferably, in the modulation circuit of the present invention, for each of the divided binary codes, the selecting means divides the predetermined period into a plurality of sub-frame periods of lengths corresponding to the bit lengths of the divided binary codes and selects and outputs the divided binary code corresponding to a sub-frame period in that sub-frame period.
According to the modulation circuit of the present invention employing the above configuration, the predetermined period is divided into a plurality of periods corresponding to the divided binary codes. The periods obtained by the division are defined as sub-frame periods. Each sub-frame period is set to have of a length corresponding to the bit length of the divided binary code corresponding to the sub-frame period. The divided binary codes are output by the selecting means to the pulse output means in the sub-frame periods corresponding to the divided binary codes.
Preferably, in the modulation circuit of the present invention, when the bit length of the i-th (i is a natural number) divided binary code from the least significant bit of the binary code is B(i) (B(i) is a natural number), the pulse outputting means sets the level of a pulse signal corresponding to the (i+1)-th divided binary code from the least significant bit of the binary code to a magnitude of 2 to the B(i) power (2B(i)) times the level of the pulse signal corresponding to the i-th divided binary code.
According to the modulation circuit of the present invention employing the above configuration, the level of a pulse signal is set corresponding to the respective divided binary code. The level of a pulse signal is defined by the relation with the level of the pulse signal corresponding to the next lower divided binary code of the divided binary code corresponding to the pulse signal. That is, the level of a pulse signal corresponding to the (i+1)-th divided binary code from the least significant bit of the binary code is set to a magnitude of 2 to the B(i) power (2B(i)) times the level of the pulse signal corresponding to the i-th divided binary code.
Preferably, in the modulation circuit of the present invention, there is provided a clock counting means for receiving clock pulses, counting the clock pulses from an initial value at the beginning of each sub-frame period, and outputting the clock count. The pulse outputting means detects the time when the magnitudes of the clock count and the value of the divided binary code invert and inverts the level of the pulse signal near this time.
According to the modulation circuit of the present invention employing the above configuration, the clock counting means counts the clock pulses from an initial value at the beginning of each sub-frame period. The pulse outputting means compares the obtained clock count output by the clock counting means and the value of the divided binary code and inverts the level of the pulse signal when the magnitude of the clock count and the value of the divided binary code invert.
According to a second aspect of the present invention, there is provided an image display comprising a selecting means for dividing a binary code into a plurality of binary codes from the most significant bit to the least significant bit and selecting and outputting the divided binary codes produced by the division in a preset order, a pulse outputting means for receiving the divided binary codes from the selecting means and outputting a plurality of the pulse signals having pulse widths and levels corresponding to the divided binary codes at a predetermined period, and light emitting elements emitting light of luminances corresponding to the levels of the pulse signals.
According to the image display of the present invention, the binary code for modulating the pulse signal is divided into a plurality of codes from the most significant bit to the least significant bit. The plurality of binary codes obtained by this division are defined as divided binary codes. These divided binary codes are selected and output to the pulse outputting means in a preset order by the selecting means. Then, the pulse outputting means generates and outputs a plurality of pulse signals having pulse widths and levels corresponding to the divided binary codes at a predetermined period. The pulse signals are input to the light emitting elements, then the light emitting diodes emit light at luminances corresponding to the levels of the pulse signals.
Preferably, in the image display of the present invention, for each of the divided binary codes, the selecting means divides the predetermined period into a plurality of sub-frame periods of lengths corresponding to the bit lengths of the divided binary codes and selects and outputs the divided binary code corresponding to a sub-frame period in that sub-frame period.
According to the image display of the present invention employing the above configuration, the predetermined period is divided into a plurality of periods corresponding to the divided binary codes. The periods obtained by the division are defined as sub-frame periods. Each sub-frame period is set to have of a length corresponding to the bit length of the divided binary code corresponding to the sub-frame period. The divided binary codes are output by the selecting means to the pulse output means in the sub-frame periods corresponding to the divided binary codes.
In the image display of the present invention, when the bit length of the i-th (i is a natural number) divided binary code from the least significant bit of the binary code is B(i) (B(i) is a natural number), the pulse outputting means sets the level of a pulse signal corresponding to the (i+1)-th divided binary code from the least significant bit of the binary code to a magnitude of 2 to the B(i) power (2B(i)) times the level of the pulse signal corresponding to the i-th divided binary code.
According to the image display of the present invention employing the above configuration, the level of a pulse signal is set corresponding to the respective divided binary code. The level of a pulse signal is defined by the relation with the level of the pulse signal corresponding to the next lower divided binary code of the divided binary code corresponding to the pulse signal. That is, the level of a pulse signal corresponding to the (i+1)-th divided binary code from the least significant bit of the binary code is set to a magnitude of 2 to the B(i) power (2B(i)) times the level of the pulse signal corresponding to the i-th divided binary code.
In the image display of the present invention, there is provided a clock counting means for receiving clock pulses, counting the clock pulses from an initial value at the beginning of each sub-frame period, and outputting the clock count. The pulse outputting means detects the time when the magnitudes of the clock count and the value of the divided binary code invert and inverts the level of the pulse signal near this time.
According to a third aspect of the present invention, there is provided a modulation method for dividing a binary code into a plurality of binary codes from the most significant bit to the least significant bit and generating a plurality of pulse signals modulated in accordance with the divided binary codes at a predetermined period, comprising a first step of selecting one of the plurality of divided binary codes and a second step of generating a pulse signal having a pulse width and level corresponding to the divided binary code selected in the first step in a period of a length according to the bit length of the divided binary code, wherein the first and the second steps are repeated in the predetermined period while selecting the divided binary codes in a preset order.
According to the modulation method of the present invention, the first step selects one of the divided binary codes obtained by dividing the binary code into a plurality of binary codes from the most significant bit to the least significant bit. The second step generates a pulse signal having a pulse width and level corresponding to the divided binary code selected in the first step in a period of a length according to the bit length of the divided binary code.
The first step selects the divided binary codes one by one in a predetermined order. Each time the first step selects a divided binary code, the second step generates a pulse signal according to the divided binary code selected at the first step. In this way, the first and the second steps are repeated in the predetermined period.
In the modulation method of the present invention, when the bit length of the i-th (i is a natural number) divided binary code from the least significant bit of the binary code is B(i) (B(i) is a natural number), the second step sets the level of a pulse signal corresponding to the (i+1)-th divided binary code from the least significant bit of the binary code to a magnitude of 2 to the B(i) power (2B(i)) times the level of the pulse signal corresponding to the i-th divided binary code.
According to the modulation method of the present invention employing the above configuration, the second step sets the level of a pulse signal corresponding to the respective divided binary code. The level of a pulse signal is defined by the relation with the level of the pulse signal corresponding to the next lower divided binary code of the divided binary code corresponding to the pulse signal. That is, the level of a pulse signal corresponding to the (i+1)-th divided binary code from the least significant bit of the binary code is set to a magnitude of 2 to the B(i) power (2B(i)) times the level of the pulse signal corresponding to the i-th divided binary code.